1. Field of the Invention
The present invention relates to a layout of word lines of a nonvolatile semiconductor memory.
2. Description of the Related Art
A nonvolatile semiconductor memory, in particular, a NAND cell type flash memory has been recently used as a main memory of a variety of electronic devices such as a portable audio device by utilizing features such as large capacity and nonvolatile properties.
Under such a circumstance, in the NAND cell type flash memory, in addition to improvement of its function, further increasing its capacity is a problem to be solved.
In order to achieve a NAND cell type flash memory with a large capacity, promoting downsizing of memory cells is the simplest method, whereas there exists an obstacle associated with the minimum processing dimension of a resist in an exposure device in order to downsize the memory cells.
For example, a size F (future size) of the memory cells in a direction parallel to a NAND string is determined by half of pitches of word lines (half pitches), whereas the half pitches generally cannot be smaller than the minimum processing dimension.
Therefore, a downsizing processing technique to achieve a size smaller than the minimum processing dimension from the viewpoint of process is proposed in each of document 1 (Jpn. Pat. Appln. KOKAI Publication No. 5-88375) and document 2 (Jpn. Pat. Appln. KOKAI Publication No. 8-55920).
This downsizing processing technique is featured in that an undercoat is processed using a side wall as a mask.
However, only forming a line & space pattern is disclosed in document 1, and there is no discussion of actually applying this pattern forming to a nonvolatile semiconductor memory. That is, in the downsizing processing technique utilizing the side wall, even if a line & space pattern can be formed, a contact hole cannot be formed.
Therefore, even if a fine line & space pattern has been formed, a contact cannot be brought about with respect to each pattern. Thus, for example, word lines of the nonvolatile semiconductor memory cannot be provided.
In contrast, in document 2, there is proposed a downsizing processing technique that presumes application to word lines. According to this technique, word lines are processed using a side wall as a mask and fringes are alternately formed at both ends of the word lines, thereby allocating a contact area relevant to the word lines.
However, in such a layout, the fringes are directly connected to both ends of the word lines, thus making it difficult to form fringes of sufficient size. In addition, even if the fringes are alternately connected to both ends of the word lines, and further, the fringes at one end of the word lines have been laid out in a zigzag manner, the size of the fringe is still influenced by the pitches of the word lines.
Therefore, as the pitches of the word lines become narrow, a fringe having a sufficient size cannot be formed. In addition, there occurs a problem associated with an increase in contact resistance when an alignment shift between the fringe and the contact hole occurs or short circuit between the adjacent word lines in the worst case.